<Controller>ڵ㣺
Backend_Mode								: 0: tx_mode_noneֺ֧; 1: tx_mode_BackendɷͶFPGAоƬĿ; 2: tx_mode_NICǧģʽFPGAоƬֱӽտĿ
															      3: tx_mode_RxcɽնFPGAоƬĿ; 
															      
<Common>ڵ㣺
FpgaLOGOSupport							:	ɽնǷ֧LOGOʾY04Y08C04C08ָ֧ùܣ0֧֣1֧
FrontScreenSupport					:	ɽնǷ֧ǰܣҪӦڳ⳵0֧֣1֧

<Backend>ڵ㣺󼶷/ն˹Եýڵ㣨һ󼶽ڵɶӦͬǰͺţӦϵܱУ

Controller_Type							: 򲥷ǰоƬͺţͿController_TypeͬFPGA_Type
Controller_Name							: ƣڽʾļ
FPGA_Type										: ɺFPGAоƬͺţһ㼯ɷͶFPGA_Class=0նFPGA_Class=1Ϊ0ʾ޼FPGAоƬ
FPGA_Class									: FPGAоƬͣ0Ͷˣ1նˣ3๦ܿ8ƵܻͬڷͶˣ
TxcFPGA_Count								: ɷͶFPGAоƬĸĬϣ1=0PortCount>0ʱʾΪǧģʽֽ֧տӲַ֧Ͷã
Port_Count 									: ֿ֧ӽտڸTXCFPGA_Count>1ʱÿFPGAоƬֵ֧ڸFPGA_ListбΪ׼ǰͶ˲еоƬ֧ڸΪ8
VSM													: Ƿ֧VSMЭ飻0֧֣1֧֡VSMЭУ
															1. ֧RAM0x800ַȡMCUڲǰһЩ״ֵ̬
															2. ֧ReConfigMCUFPGAĵùܣͬʱá
															3. ֧VSMʽýֹڵĹܷʽ
															4. ֧MCUܡ
															5. ֧ͿRAM6ܡ
															ͬʱ֧VSMЭ飬MCUķͶˣĿڡʱ㹤ĿRunTime0RunTime1FlashֶϢ
PortAddressVersion					: Ͷڵַ䣨Port_Count>0ʱЧĬֵ0ģʽھɰ淢ͿڵַVSVHEVSML1XL2XM2XFPGAжøͷ࣬Ŀַbit[13,12]ʾš
																												1ģʽM4XH8XȴͿø͵ַ䣬PHY1ĵ8ֽʾţ1ʼ

TV:
FixLcd_Origin								: LCDʾʾǷ̶(0,0)ʼ1̶0½ƫơ
OldVersionPortLimit     		: ɰտ߶ƣǷַ֧ſĸ߶ȣӰ汾ŵBit4.0÷Ϳ߶Ȳơ1÷Ϳɰ߶ơĿǰֻBX-VSòΪ1ͺŶΪ0.
CopyAttribData							: ɰ淢ͿRAMĵ128256ֽڣ0127ֽݡŻƽȷϣVSML1X,M2X,4XԺͲˡ0Ҫƣ1Ҫơ˲ĬΪ0Ժͺſɲʾԡ
Support_3D									: Ƿ֧3Dʾ0֧֣1֧
PortAreaAlgorithm						: Ϳ㷨
															060Hzµȴڵڸ߶ʱΪ1280 * 512Сڸ߶ʱΪ1280 * 512 * 99.6%
															1㷨Ϊ ÿЭ鿪56ֽڣ* ڸ߶*ÿзְ+ڿ*ڸ߶*3 + ͬ900ֽ+ÿЭ鿪56*60֡/125000000  Сڵ0.989
Max_Area                    : 
FPGA_X_Increment						: оƬʼXıĬΪ0ʾҪб
PortMax_Width								: Ͷ˵ؿ
PortMax_Height							: Ͷ˵ظ߶
PixIncSelf									: ͶڵPix_IncǷ񵥶ã0ͳһãĬֵ1á

Protocol_Series							: Э汾ţ1һЭ飻Ĭϣ2Э飻һЭ飬տֶ֧룻ֶ֧㲥ʽͨѶֶ֧ʽ̼ѯ̼бܡֲ֧ѯROMϢ
Function_Series							: տܴϵУ1һĬϣ2ܴ룻0x200ʼ
SupportROM									: Ƿ֧ROMһЭ汾Ŵڵ2ָ֧ùܡ
Lattice_ECP5U								: ʱˣLattice̼л̼Ҫϵǡ
PortMin_Width								: ͿСȡ
EDID_ReConfig								: ͿEDIDúǷҪFPGAReConfig粻ҪҪԽӦĴ¸λĿǰVSML2XM2XL1XM1XEDIDʱּ֧ĴλҪReConfig
EDID_Data_Ord								: ȡEDIDţûиֶĬΪ0иֶΰճж壬ڵ1ΪVSA_Edid_Data
Max_APP_Count								: ֵ֧APP
Fcg_Mode_Addr								: лFCGĵַͿлЭ̼ĵַ
Fcg_Mode_Sector							: лFCG
FcgHeaderEnabled						: FCGǷFCGͷϢ01Ĭ1
bFactoryApp									: Ƿڳ01Ĭϣ1Ŀǰֻ4XĲϢ

Chip_ID											: ʾ˾ͣΪͨùʱͳһʾΪ 0
Chip_ID_Sub									: ǰ˾µͣͨһʱͬĴʱΪһġ
Chip_ID_Ord									: ǰ˾µšòһ˾ڣֵΨһġ

PortBackupSupport						: ֧ڱݹܣ

PixIncSelf_V4								֧V4ͶڵPixInc㷨
AudioPort										Ƶţ0ʼ¼ںţڼá,ֿ
bDiffFPGAArea								: оƬԴһ±: 
															true: ͬоƬͬ˸оƬڵĽտͬһе; 
															false: оƬͬڵĽտеá

TW:
Fixed_DVIFrame  						: ֡ʽ1̶֡ʡ֡Ϊֶ֡DVIFrame0YQ5Eʽ֡ʷʽ26Q2ʽ֡ʷʽ
Def_DispMode      					: Ĭϵʾģʽ0ͨʾģʽ1ˢʾģʽ254:6QL6ʾģʽ255:5˫ɫ͵ʾģʽ
Self_ModuleType							: ɨǷԼʾͣУɨ跽ʽеĻɹûѡûУ򲻿ѡֻܴǰ˻ȡ1ԼĻͣ0ûԼĻ

<FPGA_List.FPGA>ӽڵԣTxcFPGA_CountԴ1ʱЧ
Port_Count 									: FPGAоƬֿ֧ӽտڸFPGAб˳ۼӣǰͶ˲еоƬ֧ڸΪ8
Max_Area                    : Ͷ˵оƬ

RegStatus_List							: Ͷ˵оƬ״̬Ĵĵַб
WidthChannelMax							: ִ֧ͨصûиԱʾ֧1024㡣
Channel8Max									: Ƿ֧֧8ͨܡûиԣʾ֧֡
