<Controller>ڵ㣺ܱ豸ڵ㣬豸ͺϵкЭܵĹؼǰ/󼶵ĹòܱӣڶӦļֱӦĽڵӻרýڵ㣩
ͨ
Controller_Type							: >0: ͺţʶ豸ͺŵĹؼʶ豸ͺֵظ
Controller_Name							: ƣ豸ͺŵַʶڶӦͺŷֱļ
														ע򲿷ַ֧ʶ𣬽ʾʱת루GetRealControllerName:","Ӧ"/";"Rev "Ӧ"Rev."
Controller_Code							: ؼ֣豸еĵ2λ6λʶ豸ͺ
														עͿտϵݲ֧֣
																	ϵдڲ죺ƵͺŴڶؼ֣<BarCode_List>ڵУʡԣ
																	
Ƶר
Controller_SubCode					: Ƶӹؼ֣豸еĵ13λڲֿһ½һʶ豸ͺ
														עΪ"0"ַ򲻴ʱУӹؼ֣
OVP_Protocol								: ƵЭ
														 -1(OVP_PROTOCOL_NONE): ЧЭ
														  0(OVP_PROTOCOL_L): 		OVP_PROTOCOL_LOVP-L/MϵУOVP-L1,OVP-M1,OVP-M2,OVP-M3°֧֣
														  1(OVP_PROTOCOL_H1): 	OVP-H1°֧֣
														  2(OVP_PROTOCOL_HX): 	OVP-HX/HDϵУOVP-H8X,OVP-H4X,OVP-H4D
														  3(OVP_PROTOCOL_MX): 	OVP-MX/MD/HXLϵУOVP-M4X,OVP-M4D,OVP-L4X,OVP-M2X,OVP-M2D,OVP-L2X,OVP-M1X,OVP-L1X,OVP-H8XL,OVP-H4XL,OVP-H2XL
														  4(OVP_PROTOCOL_G): 	  OVP-GϵУOVP-G32,OVP-G24,OVP-G16
																	
ר
FPGA_Type										: >0: ɺFPGAоƬͺ; 0: ޺豸
														עһǰ豸ɶӦͺţ<Backend_List>ڵд<controller>豸ڵдʡԣ
FPGA_Class									: ͬͨѶЭеЭ
														  0x00(BX_FPGACLASS_TXC): Ϳ/ɷͶ˵ƵĬΪǰ
														  0x01(BX_FPGACLASS_RXC): տ/ɽն˵
														  0x03(BX_FPGACLASS_MFC): ๦ܿ
														  0x08(BX_FPGACLASS_OVP): Ƶ
														  0xFE(BX_FPGACLASS_NONE): ЧЭ
														עFPGA_TypeΪ0ֵЧ
Backend_Mode								: ģʽ
															0(BACKEND_MODE_NONE): 		ֺ֧; 
															1(BACKEND_MODE_BACKEND):	ɷͶFPGAоƬĿ; 
															2(BACKEND_MODE_NIC): 			ǧģʽFPGAоƬֱӽտĿ
															3(BACKEND_MODE_RXC): 			ɽնFPGAоƬĿ; 
<Backend>ڵ
FPGA_Name										: ͺƣͺŵַʶڶӦĺ󼶷ֱļ
														ע󼶷ֱڵ豸ֱļУֱʹController_NameַʡԣַתController_Nameעͣ

